TP4 schematic
TP 4000
The TP4000 is the main switch used by PSS
A typical microcomputer consists of:
- A Central processing unit (CPU) ie the microprocessor chip
- Read only memory (ROM) which is permenent memory not lost when the power is switched off, this would normally contain the computers program
- Random Access Memory (RAM) - This can be written to and read from by the CPU, the contents of the RAM are lost when the power supply is swiched off.
- Input / Output (I/O) might include Universal Asynchronous Receiver / Transmitter chips (UART) or Serial Input / Output
- SIO or High Level Data Link Control (HDLC)
TP4000 Architecture
The TP4000 uses microprocessors (6502 chips) but it has a number of
special features:
* It uses multiple Microprocessors, each card has its own 6502
chip with its own RAM and ROM, but it also has access to a large
bank of common RAM which it can read from, and write too, via
a common bus
CPU card LPU card LPU card
______ ______ ______
| | | | | |
| CPU | | CPU | | CPU |
| | | | | |
|______| |______| |______|
__|___ __|___ __|___
| | | | | |
| ROM | | ROM | | ROM |
| | | * | | * |
|______| |______| |______|
__|___ __|___ __|___
| | | | | |
| RAM | | RAM | | RAM |
| | | * | | * |
|______| |______| |______|
__|___ __|___ __|___
| | | | | |
| I/O | | I/O | | I/O |
| | | | | |
|______| |______| |______|
|___________________|______________________|________ bus
|
_____|______
| | controls access to main memory
| Arbitrator | also contains:
| | ROM
|____________| Straps , Watch dog timer
_____|______
| |
| RAM |
| 256 K |
|____________|
Information Exchange between cards is always via the common memory
- low speed LPUs (Async cards) have no RAM/ROM, They use main memory.
- The programs for the microprocessors are contained in RAM, the ROM
contains just enough program to make a call to the network management
centre and load the rest of the program into RAM located on the arbitrator.
Hardware backup
The TP4000 is designed to continue running in case of any single
component failure
CPU,Arbitrator and Bus are all duplicated. Line cards are backed up on a 1 in N basis.
Diagram MK2 box
MK 1 box
The mark 1 boxes used Telenet Chassis, with Plessey supplying the metal rack and alarm relays.
MK2 box
Similar to mark one but plessey supply power supply etc.
MK3 box
Different layout, power supplies at bottom of rack.
Diagram MK3 box
TP4000
The TP4000 is a purpose designed packet switching unit. It was
first introduced in 1979 and has since been subject to a programme
of development and enhancement, although still based on (now very
old) 6502 microprocessor this development has allowed a large
number of software and hardware products to be built up to manage
the network.
Main Memory
The main memory is organised into two separate banks each having
a capacity of 256K bytes. Each memory bank is controlled by an
arbitrator which organises the data transfers between it's memory
and one or other of the system busses.
CPU
The CPUs are 6502 microprocessor based.
The CPUs are used to control the TP4000 and to handle the switching.
Each CPU has 128K of dedicated local memory, so that substantial
processing can be handled by the CPU's alone, with the main memories
being used only for data buffering and infrequently accessed error
recovery routines. High speed communication between the CPUs can
take place through the intra CPU link
LPU
The LPUs are 6502 microprocessor based.
Each LPU drives a number of lines, up to 8, handling the protocol
and transmitting packets to and from the main memory. Several
types exist , the HDLC LPU, is used to support X25 terminals.
Each LPU is interfaces independantly to the two busses and can
operate equally well on either bus. Each LPU has its own microprocessor
and 8Kb of local memory which enables it to handle most of the
high speed processing for the communication lines it supports.
The communication line inputs and outputs are at TTL levels and
so interface cards are used to convert to the voltages required
for V.24 and V.35 operation.
Some types of interface cards contain logic switches which normally
route the interface signals from the modems into the associated
LPU, but, if the LPU fails, they can route the signals to a switch
bus which terminates a backup LPU.
All LPUs may be removed or inserted during normal operation of
the system, so the back up unit would only be in use for a short
time until the failed unit is replaced.
Interface modules buffer the line connections to the LPUs and
provide the appropriate X21 bis interfaces.
Redundancy is provided by a full back-up of the common modules
ie CPU, TX2 memory, arbitrator and bus and by a configurable 1
for N, LPU redundancy.
The TP4000 is designed for unattended operation, having comprehensive remote management facilities.
Software loading, fault reports and diagnostics are all performed from a centralised Network Management Centre (NMC). The NMC can designate one of up to four software releases to loaded into any TP4000.
To: TJT009
To: D.YIP (TJT011)
To: TJT094
To: NMCC.M (TJT096)
To: NETOB.MH (TJT112)
To: T.DAWSON (TJT115)
To: A.TAYLOR (TJT117)
To: E.MCDONNELL (TJT119)
To: B.EVANS (TJT121)
To: G.ISBELL (TJT122)
To: ROTA.1 (TJT131)
To: ROTA.2 (TJT132)
To: ROTA.3 (TJT133)
To: ROTA.4 (TJT134)
To: R.CRISP (TJT135)
To: NMCC.L (TJT137)
To: NMCV.L (TJT138)
To: TOA.LB (TJT140)
To: J.SMITH (TJT142)
To: NMCA.L (TJT143)
To: D.WILSHER (TJT147)
To: MANCHESTER (TJT149)
To: TOA.M (TJT150)
To: NMCA.M (TJT151)
To: M.LEWIS (TJT152)
To: R.NELSON (TJT365)
To: A.KING (TJT369)
To: G.CLEWLOW (TJT373)
To: W.PARKINSON (TJT377)
To: I.KALKAT (TJT399)
To: B.WRIGHT (TJT400)
To: MANCH.CSG (TJT406)
To: T.MOORE (TJT419)
To: NETOB.MC (TJT421)
To: B.FERNANDEZ (TJT488)
Cc: M.BAKER (TJT106)
Cc: B.BARKER (TJT124)
From: T.DAWSON (TJT115) Delivered: Mon 21-Dec-87 15:17 GMT Sys 10085 (52)
Subject: Intro. of Network Release 3.20 - Stage 2
Mail Id: IPM-10085-871221-137660615
To: NMC, CSG.TB and OMGC
As from Monday December 21st, the CSG will be Table Building on NMCA
ONLY. Parallel table building on NMCB ceases and this machine will
be upgraded to Network Release 3.2 to act as a standby loader for NMCA
generated 3.20 tables.
The point of NO RETURN - hence it is IMPORTANT to look out for the
known problems ( viz missing TP Save's and unloaded PVC's ) and take
the necessary preventive/corrective action.
The 'Save and Restore' procedure for the NMC will differ, as from
December 21st, in that the Save's will be to tape again. Procedure
as follows -
(a) Open 'Save and Restore' Como.
(b) Run Save ( to tape ) on NMCA - commands,
A BUILD
R *SAVE_TABLE TTY
(c) Run Restore ( from tape ) on NMCB - commands,
A TRANSFER
R *RESTORE_TABLES BA A02 NB TTY
( static only restore - secondary load machine )
(d) Run Restore ( from tape ) on NMCA - commands,
A TRANSFER
R *RESTORE_TABLES A02 NB TTY
( dynamic restore - primary load machine )
(e) Close Como's
If anyone can foresee any problems or has any questions regarding any
of the above. Please phone.
Regards,
Terry Dawson
PDN/SO/TS
01-250 8857
NB - The third and final stage of this part of the Network Release 3.20
migration plan takes place on January 4th - NMCB will be the Table
Building and Primary Load machine with NMCA as Secondary Load
machine only.
|
From: M.BAKER (TJT106) Delivered: Fri 16-June-89 16:03 BST Sys 10085
To: K.JOSEPH (TJT040)
Subject: 3.52 rollout restart
Mail Id: IPM-10085-890616-144460326
Telenet release 3.52 - main engine start
----------------------------------------
The next stage of the 3.52 configuration tables has now been rescheduled
for Sunday, This has been agreed in conjunction with DN/O/NM1 and CSG
(Reg). Instructions to the NMC + any change control required, for the
Sunday load, will be issued through the normal channels by DN/O/NM1.
The purpose of this message is just an additional warning that these 3.52
loads include some distribution level boxes which have X.25 and
Asynchronous customer lines.
NMC rota: please follow the change control + Bernards notes which I sent
out on Tuesday. Please send Bruce and me a Gold to let us know how it
went.
All: Please keep a special check for any X.25 or asynchronous faults on
the Colombo TPs concerned.
Martin Baker
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Further Information
Other X.25 Equipment
Other PSS related pages
